Skew Minimization with Low Power for Wide Voltage Range Using Course Grain Technique

Skew is one of the most important parameter that decides the performance of the system. Though skews are reduced using two-stage(low and high voltage levels) serially connected power mode aware buffers(PMABs) using two power gating techniques-Fine grain technique at high voltage level and Coarse grain technique at low voltage level, the power consumption and area is large incase of fine grain technique. So, in the proposed system, coarse grain minimization is used at both stages which will effectively reduce power consumption and area. The coursegrained approach implements the grid style sleep transistors which drive cells locally through shared virtual power networks. This approach is less sensitive to PVT variation, introduces less IR-drop variation, and imposes a smaller area overhead than the cellor clusterbased implementations. In coarse-grain power gating, the power gating transistor is a part of the power distribution network rather than the standard cell.